1. Field of the Invention
The present invention relates to a stackable semiconductor package, and more particularly, to a stackable semiconductor package including at least one supporting element for supporting.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a cross-sectional schematic diagram showing a prior art stackable semiconductor package. The prior art stackable semiconductor package 1 includes a first substrate 11, a chip 12, a second substrate 13, a plurality of wires 14 and a molding compound 15. The first substrate 11 has a first surface 111 and a second surface 112. The chip 12 connects to the first surface 111 of the first substrate 11 by means of flip chip technology. The second substrate 13 is adhered to the chip 12 by an adhesive layer 16. The second substrate 13 has a first surface 131 and a second surface 132, where the first surface 131 has a plurality of first bonding pads 133 and a plurality of second bonding pads 134 thereon. In top view, the area of the second surface 132 is larger than the area of a surface of the chip 12. This makes some portions of the second substrate 13 extend beyond the chip 12, and become an overhang portion.
The wires 14 electrically connect the first bonding pads 133 of the second substrate 13 to the first surface 111 of the first substrate 11. The molding compound 15 encapsulates the first surface 111 of the first substrate 11, the chip 12, the wires 14 and parts of second substrates 13. The second bonding pads 134 on the first surface 131 of the second substrate 13 are exposed by the molding compound 15 to form a mold area opening 17. Usually, the prior art stackable semiconductor package 1 can further stack another package 18 or other components in the mold area opening 17, where the bumps 181 of the package 18 electrically connect the second bonding pads 134 of the second substrate 13.
The disadvantages of the prior art stackable semiconductor package 1 are described as follows. First, parts of the second substrate 13 are hung. The first bonding pads 133 are located on a region (that is the overhang portion), which is relatively outside the chip 12, and the horizontal distance between the first bonding pads 133 and the edge of the chip 12 is defined as a overhanging length L1. Shown by experimental data, once the overhanging length L1 is three times longer than the thickness T1 of the second substrate 13, the overhang portion shakes or sways during the wire bonding process, and it therefore causes difficulties in wire bonding. Moreover, if the second substrate 13 suffers a huge stress during the wire bonding process, the second substrate 13 might even crack. Secondly, due to the above-mentioned shake, sway or crack, the overhang portion can not extend too far from the edge of the chip 12, and the area of the second surface 132 is therefore restricted. As a result, the layout space of the second bonding pads 134, which is exposed by the mold area opening 17 on the first surface 131 of the second substrate 13, is limited. Finally, in order to reduce the occurring of the above-mentioned shake, sway or crack, the second substrate 13 cannot be too thin. Thus, the whole thickness of the prior art stackable semiconductor package 1 cannot be reduced effectively.
Accordingly, a stackable semiconductor package having originality and advancement is needed to solve the above-mentioned problem.